About the Role
As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you.
What You'll Do
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Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.
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Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.
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Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.
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Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.
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Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.
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Grow and mentor the silicon team as the company scales.
What We're Looking For
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8 or more years of hands-on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.
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Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.
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End-to-end FPGA experience: RTL through synthesis, place-and-route, and deployment to working hardware.
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Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.
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Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.
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Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.
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Background designing or optimizing AI accelerators or low-level AI kernel implementations.
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Tapeout experience, high-speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.
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Self-directed, comfortable with ownership, and energized by fast-moving environments.
Compensation & Benefits
Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available.
Location
Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.
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