Responsible for Design and development of critical analog, mixed-signal, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Su…
InfosysActive opening
Analog Layout
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analog layoutmixed-signallvsdrcantenna checks
InfosysAnalog Layout
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