FPGA Engineer

About O-HIVE

O-HIVE is a technology company developing advanced Visual Language Models (VLMs), spatial intelligence, and edge AI solutions for robotics, industrial automation, autonomous systems, and intelligent inspection.

Our technology enables machines to perceive, interpret, and interact with the physical world through visual intelligence, object detection, spatial mapping, and real-time decision-making.

We are developing a dedicated Spatial Vision AI System-on-Chip (SoC) architecture that integrates hardware-accelerated visual processing, Simultaneous Localization and Mapping (SLAM), object detection, and VLM inference into compact, power-efficient computing platforms.

Position Overview

We are seeking an FPGA Engineer to design, implement, and optimize hardware acceleration architectures for O-HIVE's next-generation Spatial Vision AI platforms.

The successful candidate will translate existing computer vision and AI algorithms into efficient FPGA implementations, with a focus on real-time performance, low-latency processing, memory efficiency, and power optimization.

This role involves working closely with AI researchers, embedded software engineers, and ASIC design engineers to develop FPGA-based prototypes and hardware architectures that can ultimately transition into custom silicon.

The ideal candidate combines strong digital logic design capabilities with an understanding of computer vision, hardware acceleration, and embedded computing systems.

Key Responsibilities1. FPGA Architecture & Development

• Design and implement FPGA-based hardware accelerators using Verilog, SystemVerilog, VHDL, or High-Level Synthesis (HLS).
• Develop efficient hardware architectures for high-throughput and low-latency image and AI processing.
• Implement pipelined, parallel, and resource-optimized computing architectures.
• Optimize FPGA designs for logic utilization, DSP resources, memory bandwidth, timing, and power consumption.
• Develop reusable IP cores and hardware modules suitable for future ASIC integration.
• Support FPGA prototyping, hardware validation, and system-level performance optimization.

2. Computer Vision & AI Acceleration

• Implement hardware acceleration for computer vision algorithms, including feature extraction, image preprocessing, and visual perception.
• Accelerate SLAM-related operations, including ORB feature extraction, feature matching, and geometric processing.
• Develop FPGA acceleration architectures for object detection and neural network inference.
• Support quantized AI computation, including INT8, INT4, FP8, and other numerical representations as appropriate.
• Optimize data movement, buffering, and memory access patterns for image-processing and AI workloads.
• Collaborate with AI engineers to translate software algorithms into hardware-efficient implementations.

3. Sensor Integration & Real-Time Processing

• Develop FPGA interfaces for image sensors, including MIPI CSI-2 and other high-speed camera protocols.
• Implement real-time image-processing pipelines for preprocessing, filtering, and data formatting.
• Integrate IMU and other sensor inputs for synchronized visual processing.
• Develop hardware-level timestamp synchronization and sensor data processing.
• Support image stabilization, motion compensation, and sensor-fusion preprocessing.
• Interface FPGA accelerators with embedded processors, external memory, and peripheral devices.

4. Embedded Systems & Hardware Integration

• Develop and validate FPGA applications on AMD/Xilinx and other suitable FPGA platforms.
• Work with ARM-based embedded processors and heterogeneous SoC architectures.
• Implement high-performance communication between FPGA logic, CPU subsystems, and memory.
• Integrate FPGA components with Linux-based embedded software and C/C++ applications.
• Perform hardware debugging, system testing, and performance profiling.
• Collaborate with PCB, embedded, and hardware engineering teams to integrate FPGA modules into compact computing systems.

5. ASIC Development & Design Transition

• Develop FPGA architectures with consideration for eventual ASIC implementation.
• Collaborate with ASIC engineers to transition validated FPGA designs into synthesizable RTL.
• Support architecture evaluation, RTL verification, timing analysis, and design optimization.
• Prepare hardware documentation, test environments, and performance benchmarks.
• Assist with functional verification and hardware/software co-design.
• Contribute to the development of low-power, high-performance spatial intelligence processing architectures.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Strong understanding of digital logic design and FPGA architecture.
• Experience with Verilog, SystemVerilog, or VHDL.
• Hands-on experience with FPGA development platforms and design tools such as AMD/Xilinx Vivado, Vitis, or Intel Quartus.
• Knowledge of RTL simulation, functional verification, synthesis, and timing closure.
• Familiarity with embedded systems, ARM processors, memory interfaces, and hardware communication protocols.
• Working knowledge of C/C++ and Python for hardware validation and algorithm integration.
• Understanding of pipelining, parallel processing, fixed-point arithmetic, and hardware resource optimization.
• Strong analytical and problem-solving skills.
• Ability to work collaboratively across hardware, software, and AI development teams.

Preferred Qualifications

• Experience accelerating computer vision or machine learning algorithms on FPGA platforms.
• Familiarity with SLAM architectures, particularly ORB-SLAM2, ORB-SLAM3, or related visual odometry algorithms.
• Experience implementing feature extraction, feature matching, convolution, or matrix operations in hardware.
• Knowledge of AI inference optimization and quantization techniques.
• Experience with MIPI CSI-2, image signal processing (ISP), or high-speed camera interfaces.
• Familiarity with AMD Kria, Zynq UltraScale+, Versal, or similar FPGA/SoC platforms.
• Experience with AXI interfaces, DMA engines, DDR memory controllers, and high-bandwidth data pipelines.
• Familiarity with High-Level Synthesis and hardware/software co-design.
• Exposure to ASIC design methodology, including synthesis constraints, clock-domain crossing, and power-aware RTL design.
• Experience with robotics, autonomous navigation, drones, or industrial vision systems.
• Understanding of power, performance, and area (PPA) optimization.

Key Development Objectives

The FPGA Engineer will contribute directly to the following engineering milestones:

• Spatial Vision Acceleration: Develop hardware accelerators for visual feature extraction, matching, mapping-related computation, and pose-estimation workloads.
• AI Inference Optimization: Implement and optimize FPGA-based processing components for object detection and VLM-related workloads.
• Sensor Processing: Establish synchronized image acquisition, IMU integration, and real-time preprocessing pipelines.
• Edge Computing: Improve processing latency, throughput, memory utilization, and power efficiency for embedded AI systems.
• ASIC Readiness: Deliver verified, reusable RTL architectures suitable for integration into O-HIVE's custom Spatial Vision ASIC development process.

Pay: $50,000.00-$80,000.00 per year

Work Location: In person

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