Staff ASIC Physical Design Engineer

Job Overview

As a Staff ASIC Physical Design Engineer, you’ll drive the physical implementation of application-specific integrated circuits (ASICs) and system-on-chip (SoC) designs, turning design requirements into reliable, manufacturable hardware. You’ll partner across design, verification, and manufacturing teams to resolve implementation challenges and keep project schedules moving. Your impact: By finding and resolving physical design issues early, you help teams deliver dependable silicon and enable customers to use products with confidence.

Core Technical Skills & Competencies1. EDA Tools & Implementation Flows

• Logic & Physical Synthesis: Hands-on expertise with Cadence Genus (including physical-aware synthesis and Stylus Common UI flows).
• Place & Route / Floorplanning: Deep proficiency in Cadence Innovus for macro placement, IO pin assignment, core utilization sizing, congestion mitigation, and early physical prototyping.
• Signoff & Analysis Ecosystem: Working familiarity with adjacent signoff tools for correlation (e.g., Cadence Tempus for STA, Voltus for power integrity, Quantus for RC extraction).
• Automation & Scripting: Strong TCL and Python scripting capabilities to automate synthesis/floorplan runs, parse timing/QoR reports, and manage Multi-Mode Multi-Corner (MMMC) configurations.

2. Domain & Architectural Competencies

• PPA Optimization: Ability to systematically balance and optimize Power, Performance, and Area (PPA) across synthesis and early physical implementation stages.
• Synthesis-to-Implementation Correlation: Deep understanding of wire-load vs. physical-aware modeling so timing, area, and congestion metrics in Genus accurately predict downstream Innovus P&R behavior.
• Timing Closure & Bottleneck Root-Cause Analysis: Identifying critical paths, logic depth issues, clock skew sensitivity, and routing congestion early in the RTL-to-GDSII cycle before full P&R execution.
• Constraint Management (SDC & MMMC): Writing, validating, and debugging Synopsys Design Constraints (SDC), clock definitions, timing exceptions, and PVT corner setups.

3. Process Node & Design Scale Experience

• Sub-5nm FinFET / GAA Nodes: Proven tape-out or block-level execution at N5, N3, or sub-3nm nodes, managing high cell density, strict design rules, and complex parasitic/variation effects.
• Large-Scale SoC & AI Compute Architectures: Experience handling high-instance-count, macro-heavy blocks (SRAMs, register files, high-speed interfaces) typical of AI accelerators and hyperscale SoCs.

4. Cross-Functional Collaboration Competencies

• RTL & Architecture Feedback: Translating physical synthesis and floorplan bottlenecks into actionable RTL restructuring recommendations (pipelining, mux reduction, memory partitioning) for front-end designers.
• External P&R Partner Alignment: Packaging clean handoff collaterals (synthesized netlists, floorplan DEF files, validated SDCs, UPF) and iterating with external implementation teams to drive convergence.

Pay: $70.00 - $75.00 per hour

Expected hours: 40.0 per week

Benefits:

• Flexible schedule

Work Location: In person

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