ASIC Digital Design, Staff Engineer
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Reach the decision-maker — $5About the role
What You’ll Be Doing: Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP. Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists. Perform functional verification of SERDES blocks, including TX/RX data paths, equalization algorithms, adaptation loops, CDR behavior, PLL locking, and analog/digital interaction…
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