What We're Researching
We're running a paid study on transistor-level circuit design and simulation methodologies. The goal of this ongoing technical project is to evaluate and refine automated workflows for complex circuit analysis. Your expertise will help us build more robust evaluation pipelines for modern hardware engineering.
How It Works
You will participate in a series of technical tasks involving transistor-level circuit design. The work includes running SPICE simulations and reviewing automated evaluation outputs for accuracy. You will document your findings, troubleshoot simulation errors, and provide structured feedback on the workflow performance. All tasks are completed remotely through our secure evaluation platform.
Who This Is For
We are looking for hardware engineers, IC designers, and electrical engineering professionals with strong backgrounds in circuit simulation. You should have hands-on experience writing and debugging SPICE models for transistor-level designs. We welcome analog design engineers, mixed-signal engineers, and CAD workflow specialists to apply.
What You'll Do
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Design and review transistor-level circuits for technical evaluation
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Run SPICE simulations and verify the accuracy of the outputs
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Identify and troubleshoot errors within automated evaluation workflows
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Provide structured feedback on simulation tools and methodologies
Who Should Apply
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Professional experience in electrical engineering or integrated circuit design
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Hands-on proficiency with SPICE simulation and transistor-level modeling
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Familiarity with automated evaluation workflows in hardware design
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Comfortable completing complex technical tasks in a remote environment
Compensation
$158 per hour
Ready to participate?
Start your paid interview now
About Terac
Terac is building the world's largest pool of vetted human experts for AI. Researchers, AI labs, and product teams use Terac to recruit, screen, and pay study participants across industries, languages, and skill sets.
Learn more at terac.com or on YouTube at @jointerac.
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