Locations: Ukraine, Poland, Czech Republic, Romania, Slovakia, Spain
We are recruiting a Senior Logic Design Engineer to develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology.
This hands-on R&D role involves designing configurable, low-latency hardware and collaborating with architects, verification engineers and software specialists.
DCV.CK.JO.28.10.2026
Responsibilities
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Design and implement complex SystemVerilog RTL modules.
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Develop signal processing, waveform generation and real-time control logic.
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Contribute to architecture, microarchitecture and RTL integration.
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Perform synthesis, static timing analysis and optimization.
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Debug and verify RTL functionality with verification teams.
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Integrate digital IP and hardware-software interfaces.
Requirements
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4+ years of professional FPGA/ASIC digital logic design experience.
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Strong hands-on SystemVerilog RTL development.
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Solid understanding of digital microarchitecture and synchronous design.
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Experience with synthesis, STA, timing optimization and CDC.
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Practical FPGA/ASIC implementation and RTL debugging experience.
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Confident English (B2+).
Advantages: AMD/Xilinx Versal, Vivado, Questa/VCS, DSP, high-speed interfaces, ASIC IP, Python/Tcl automation and hardware-software co-design.
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